Nonvolatile memory cells, in particular EEPROM memory devices, are programmed by biasing a memory transistor within a memory cell to predetermined values. A memory transistor is programmed to one of two states by moving electrons into (or out of) a floating gate from a channel region, via a gate dielectric coupling the floating gate and the channel region; the gate dielectric typically being an oxide.
For example, NMOS memory transistors are erased when there is a negative charge (for example, −5 Volts with respect to common or ground) on the floating gate and in a written state when there is a positive charge on the floating gate (for example, +5 Volts with respect to common or ground). In such a device, to obtain a logical “1” value (erased state), electrons must tunnel into the floating gate which increases a threshold voltage of the floating gate transistor. To obtain a logical “0” value (written state) for the same device, electrons must tunnel from the floating gate which decreases the threshold voltage of the floating gate transistor.
A desired charge level is programmed by applying an appropriate combination of voltage pulses to the source, drain, and control gate of a memory transistor, for a designated period of time, in order to move electrons to or from the floating gate. Electrons tunnel into and are trapped in the memory cell's floating gate region or electrons are removed from the memory cell's floating gate region and the memory cell threshold voltage is modified. A mechanism referred to as Fowler-Nordheim tunneling can be used for both erase and program operations, whereby a desired charge level is established in the floating gate of the memory transistor. This mechanism is very slow (in the millisecond range) and requires a high-voltage source that is typically generated by high-voltage circuits (e.g., charge pumps) within the EEPROM memory device.
Referring to FIG. 1, a prior art, NMOS floating gate memory transistor (memory transistor) 10, is comprised of a control gate terminal 11, a floating gate 12, a drain terminal 13, and a source terminal 14. The memory transistor 10 is erased to a logic value “1” by applying a high voltage (12-15 Volts) to the gate terminal 11 of the memory transistor 10 and applying a low voltage (for example, ground) to the source terminal 14. Writing a logic value “0” to the memory transistor 10 can be achieved in two steps. First, the memory transistor 10 is erased or set to a logic value “1,” as described above. Then, a high voltage is applied to the drain terminal 13 of the memory transistor 10 and a low voltage is applied to the control gate terminal 11, while the source terminal 14 is left floating. For certain embodiments in this application, a program operation will be treated as a single step, namely the second step of the previous sentence which is the inverse of the erase operation.
It is desirable to apply programming pulses that quickly program a memory cell or the memory transistor 10. However, applying a pulse with a voltage that is too high may over-program the memory transistor 10 or damage the gate oxide (not shown) isolating the floating gate 12 from a channel region (not shown) and destroy the memory transistor 10.
Generally, it is desirable to apply a high voltage pulse to the memory transistor 10 during a write operation. A high voltage, such as 15 Volts, quickly transfers electrons from the floating gate 12 and decreases the programming time for a memory cell with which the memory transistor 10 is associated. The stored charge on the floating gate 12 in combination with the applied voltage to the drain terminal 13 may cause the gate oxide to break down.
When the voltage between the drain terminal 13 and the floating gate 12 exceeds a breakdown limit, the gate oxide breaks down and the floating gate memory transistor 10 fails. A typical breakdown voltage may be 15 Volts to 20 Volts. However, as integrated circuit geometries shrink in size and gate oxide thicknesses decrease, the breakdown voltage for an individual device may decrease.
In one convention, when the memory transistor 10 is erased, a negative charge is stored on the floating gate 12. The charge stored on the floating gate 12 may be approximately −5 Volts. When a positive voltage pulse of, for example, +15 Volts is applied to the drain terminal 13 during a write operation, the voltage between the drain terminal 13 and the floating gate 12 is approximately 20 Volts, which may cause the gate oxide to break down.
Referring to FIGS. 2A-C, a 15 Volt pulse having a fast rising edge is applied to the drain terminal 13 of the memory transistor 10 of FIG. 1 (VDRAIN, FIG. 2A). The floating gate 12 is charged to −5 volts (VFG, FIG. 2B). A drain to floating gate differential voltage (VDRAIN-VFG, FIG. 2C) may exceed (e.g., as indicated by a shaded area of FIG. 2C) the breakdown voltage for the gate oxide, damaging the gate oxide and causing the memory transistor 10 to fail.
U.S. Pat. No. 6,392,931 to Pasotti et al. entitled “Method for High Precision Programming Nonvolatile Memory Cells, With Optimized Programming Speed” discloses applying a succession of voltage pulses to the control gate terminal of a selected memory cell necessary for reaching a final erase voltage value but does not address the problem of protecting the memory cell from breakdown.
U.S. Pat. No. 5,754,470 to Engh et al. entitled “Apparatus for Programming a Voltage Within a Storage Element” discloses a track and hold circuit and an integrator that determines a target voltage to be applied to a storage element. The apparatus includes a voltage ramp circuit and simultaneously reading the storage element to determine whether the storage element matches a target voltage. However, Engh only describes iteratively or repeatedly providing a plurality of write pulses and using a voltage ramp to increase the peak voltage of each successive pulse to avoid over-programming the storage cell.
It is desirable to have a stepped voltage to rapidly charge a floating gate while maintaining the charging voltage at a level that is less than a breakdown voltage for the gate oxide.